1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device for achieving high speed and low power consumption at the same time.
2. Description of Related Art
High speed performance and the low power consumption are demanded of a semiconductor integrated circuit device using a CMOS circuit. Particularly, in the CMOS circuit to be used in a battery-driven device such as a portable information apparatus, since it becomes possible to extend the battery life by reducing the power consumption, manufacturers have demanded that the power consumption be reduced. The power consumption of the CMOS circuit includes dynamic power consumption associated with charging/discharging current during a switching operation and static power consumption due to subthreshold leakage current of the MOS transistor. Since the dynamic power consumption is in proportion to square of supply voltage vdd, the power consumption can be effectively reduced when the value of the supply voltage vdd is lowered. For this reason, the supply voltage vdd has gradually become lower. Also, in the semiconductor integrated circuit devices in recent years, there are also some devices provided with a power management system which stop the supply of a clock to the execution unit during standby. Due to the stop of supply of the clock, dynamic power consumption in an idle execution unit can be reduced. However, the static power consumption cannot be reduced by this method.
On the other hand, in order to prevent deterioration in working speed associated with a drop in the supply voltage vdd, it is necessary to lower the threshold voltage of a MOS transistor together with the lowering of the supply voltage vdd. Since subthreshold leakage current increases when the threshold voltage of the transistor is lowered, static power consumption, which has conventionally been negligible, becomes increasingly significant as the supply voltage vdd is reduced. The magnitude of the static power consumption then cannot be ignored as compared with the dynamic power consumption.
As a method for solving the above-described problem, there is known a method for controlling threshold voltage of the MOS transistor by setting a body bias to be variable as has been described in, for example, 1999 International Solid-State Circuits Conference Digest of Technical Papers, pp. 280-281 (February, 1999). In an active state for performing a normal operation in which a high-speed operation of the CMOS circuit is required, the body bias is set to supply voltage vdd for the pMOS transistor (p-channel type MOS transistor), and to ground voltage gnd for the nMOS transistor (n-channel type MOS transistor). On the other hand, in a standby state in which the CMOS circuit need not operate at high speed, the body bias is set to higher voltage than the supply voltage vdd for the pMOS transistor, and to voltage lower than the ground voltage gnd for the nMOS transistor. This operation will be referred to as “body bias will be deepened” or “body bias will be made into a reverse bias” hereinafter. In an operation mode in which the CMOS circuit does not operate or a low-speed operation is allowed, it is possible to raise the threshold voltage of the MOS transistor constituting the CMOS circuit by deepening the body bias, whereby it becomes possible to reduce the static power consumption.